(1) Field of the Invention
The present invention relates to power switching metal oxide semiconductor (PSMOS) transistors, and more particularly to such PSMOS transistors which are improved so as not to be affected by stored energy flowing from an inductive load.
(2) Related Art
The power switching element of the present invention, for example, is a discrete element, and includes an output metal oxide semiconductor (MOS) transistor driven by gate electrodes, an insulated gate bipolar transistor (IGBT) or an integrated circuit comprising those elements.
A double diffused MOSFET (DMOS) is generally used as a PSMOS field effect transistor (FET), and such a DMOS is formed by contacting a plurality of unit FET cells in a row. In the case of a PSMOS transistor, for example, research and development have laid great emphasis on the basis characteristics of general devices. However, in the case where a switching element is attended with an inductive load according to the variety of applied circuits, the energy stored in a coil can be absorbed into the switching element. In the above case, since there was something remaining to study concerning the protection of such switching elements, these switching elements were often withheld from such additional use.
FIG. 1 illustrates a PSMOS transistor, and is a sectional view of a PSMOS transistor including a transistor having the structure of a vertical diffused MOS (VDMOS) and a gate electrode pad relating thereto. In FIG. 1 a portion identified by reference 100 has a first conductivity type, i.e. n-type, semiconductive substrate and serves as a drain; portions identified by reference numeral 101 have a second conductivity type opposite to the first conductivity type, i.e. p-wells, and these wells 101 are formed of more than two separated regions in the n-type semiconductive substrate 100. N-type impurity regions are formed thinly on each p-well 101 to form source regions 102. The reference letters appearing in FIG. 1 designate the following elements: (1) gate oxide films 103; (2) a field oxide film 104; (3) gate electrodes 105 formed of polysilicon; (4) inter-layer insulating films 106; (5) a source electrode 107 formed of metal; (6) a window 108 is formed to contact the source regions 102 and the source electrode. Further, a gate electrode pad 109 is deposited on the gate oxide films 103 and inter-layer insulating films 106 are double deposited on the p-wells. A drain electrode D of this VDMOS transistor is connected to the n-type substrate 100, and when this transistor is turned ON with an appropriate bias applied, a channel C is formed on portions identified by the letter "C". The n-type source regions 102 are connected to each other through the channels C between the n-type substrate 100, and the current that flows from the source regions 102 to the drain region 100 is controlled by the voltage applied to the gate electrodes 105.
In an N-channel PSMOS transistor, layers of the same conductivity as that of the well-forming region of the PSMOS transistor, i.e. the p-type impurity regions 101 are placed underneath a gate bonding pad completely separated from the source electrode 107 or another pad.
While such a PSMOS transistor is turned ON, in the case of an inductive load that is connected to this PSMOS transistor, a predetermined amount of energy is stored in the inductive load by the current thereof. However, when this PSMOS is turned OFF, the inductive load, i.e. the energy stored in the coil is released through the PSMOS transistor. At this time, a leakage current occurs by avalanche carriers formed between the n-type substrate and the p-type semiconductor layer flows to the source regions of the PSMOS transistor (MOSTR) via the base layer of a parasitic bipolar transistor within the PSMOS transistor, which is shown in FIG. 2, which is an enlarged view of the region "A" of FIG. 1. The above-mentioned parasitic bipolar transistor TR para is formed to be of an NPN type in the source regions 102, p-wells 101 and drain region 100. At this point, the current of the avalanche carrier generated from the p-wells 101 flow to the source regions 102 via the base layer of the p-wells 101. This base layer has a specific resistance R.sub.B, and a predetermined level of voltage drop is generated by the current flowing via this specific resistance R.sub.B. When the level of voltage drop is beyond a predetermined standard, a current concentration is generated by turning on the emitter-base junction of the parasitic bipolar transistor TR para, whereby the avalanche carriers current is enough to destroy this junction and flows to the source electrode 107 via the n-source regions 102 to destroy them. Accordingly, the PSMOS transistor MOSTR loses its ability to function.
In the conventional art technology, while the p-well of the channel forming portion C underneath the gate is formed with a low density, the rest is formed as a diffused region of high density to reduce a value of the base resistance R.sub.B of a parasitic bipolar transistor. In this case, there is a problem of partial turn-ON of the parasitic bipolar transistor. To solve this problem, a method for preventing a parasitic bipolar transistor from being partially turned on at the portion of the edge is disclosed in the Korean Patent Application No. 91-8714, filed 19 October 91, by equalizing the distance from an outer circumference of a second diffused region in the surface of a unit FET cell. This method, however, manages to prevent the parasitic transistor from being partially turned ON, but is not a fundamental solution preventing avalanche carriers.